1. Field of the Invention
The present invention relates to the design of a semiconductor circuit, and more specifically to a technology of creating a library used for estimating an interconnect capacitance of a circuit laid out.
2. Description of the Related Art
In recent semiconductor design, miniaturization of semiconductors, and increases in scale and speed of LSIs have been greatly improved. Conventionally (before 0.5 μm process), the circuit performance is limited by gate-specific element delay, so-called gate delay. However, Since 0.35 μm process, the circuit performance is largely influenced by interconnection delay. Thus, with a conventional method designing the logical design and the layout design separately, there may be a case where a difference arises between delay estimated at the logical design stage and delay actually measured after the layout.
As a method of estimating circuit delay at the logical design stage, a method is known which uses a tentative wire load model stored in a logical synthesis library. When the circuit delay is estimated, the tentative wire load model is read by a logical synthesis tool that executes logical synthesis. The performance of a circuit generated by logical synthesis is influenced by the accuracy of a tentative wire load model thereof. To create the tentative wire load model, statistical distribution of interconnect loads extracted from past layout results is approximated by standard deviation or the like and then it is formed into a library for each fan-out number. In the conventional logical synthesis technology, the logical synthesis tool obtains the circuit area at the initial stage of the logical synthesis, searches a logical synthesis library for a tentative wire load model (table) that matches an area condition, and obtains the interconnection (wire) load based on the fan-out number of a net (a circuit which has been laid out).
However, on an actual semiconductor integrated circuit, a plurality of nets with the same fan-out number may exist in the same placement region. In this case, even though the nets have the same fan-out number, an interconnection length of one net may be different from that of another net, because of the placements of microcells included in the respective nets. For some of the nets having a large difference between the actual interconnection length and the tentative interconnection length at the logical design stage, the accuracy in the estimation of the tentative interconnection length deteriorates.
To solve the above-described problem, Japanese Laid-Open Patent Application JP-A-Heisei, 09-134380 (1997) discloses a tentative interconnection length estimation device. The tentative interconnection length estimation device executes estimation of the tentative interconnection length in consideration of information on connection of a net targeted for estimation. This tentative interconnection length estimation device includes fan-out number reading means, target microcell pin quantity reading and determination means, target microcell net quantity reading and determination means. The fan-out number reading means is for reading information related to the fan-out number of a net targeted for estimation. The target microcell pin quantity reading and determination means is for reading information related to the pin quantity of a target microcell to be connected to a net targeted for estimation. The target microcell net quantity reading and determination means is for reading information related to the quantity of nets connected to any of the target microcells.
According to this tentative interconnection length estimation device described in JP-A-Heisei, 09-134380, the tentative interconnection length is calculated by judging whether or not it is difficult to place a first and a second target microcells adjacently to each other, and then providing different calculation methods correspondingly to the case where it is difficult to place the first and second target microcells adjacently to each other and the case where it is easy to place the first and second target microcells adjacently to each other. Therefore, estimation of the tentative interconnection length is so executed as to reduce a difference between the tentative interconnection length and the actual interconnection length of a net located between microcells that can easily be placed adjacently to each other, and a difference between the tentative interconnection length and the actual interconnection length of a net located between microcells that cannot easily be placed adjacently to each other.
However, this tentative interconnection length estimation device executes the estimation of the tentative interconnection length without considering connection relationship of each net with those located before and after thereof. When each net is connected to a large number of cells located before and after thereof, the net tends to have a long interconnection length and the interconnect capacitance thereof tends to increase. On the contrary, when each net is connected to a small number of cells located before and after thereof, the net tends to have a short interconnection length and the interconnect capacitance thereof tends to decrease.
When considering interconnection delay attributable to both the interconnection resistance and the interconnect capacitance, it is required to analyze the capacitance of a net based on the interconnection length considering whether or not cells are placed in a spreading manner or placed densely. In another word, there is a demand of a technique for analyzing the capacitance of a net in a logical circuit considering connection relationship of each net with those located before and after thereof.